My students don't use Makefile, because they it is too difficult to write. Indeed, all samples of Makefile I saw on internet are complex. This is my suggestion for a quick setup:

  bin: bin.o dependency1.o dependency2.o

And that's all! Make knows how to links object files together if one these objects has same name than final binary. And sure, it know how to convert source files to objects.

Event out-of-source build work with this Makefile:

 $ echo " bin: bin.o dependency1.o dependency2.o" >  Makefile
 $ mkdir out
 $ cd out
 $ make -f ../Makefile VPATH=..
 cc    -c -o bin.o ../bin.c
 cc    -c -o dependency1.o ../dependency1.c
 cc    -c -o dependency2.o ../dependency2.c
 cc   bin.o dependency1.o dependency2.o   -o bin

And cross-compile:

 $ mkdir out-arm
 $ cd out-arm
 $ make -f ../Makefile VPATH=.. CC=arm-linux-gcc
 arm-linux-gcc    -c -o bin.o ../bin.c
 arm-linux-gcc    -c -o dependency1.o ../dependency1.c
 arm-linux-gcc    -c -o dependency2.o ../dependency2.c
 arm-linux-gcc   bin.o dependency1.o dependency2.o   -o bin

Sure this Makefile lacks of "clean" rule, dependencies with headers, etc... but it enough for a quick test.